Basically, the reading and writing in a memory unit of an integrated circuit are processed based on stable and accurate pulses. Conventionally, the measurement of the pulse width of a pulse is realized by an on-chip jitter measurement unit as illustrated in FIG. 1. As shown, first, the leading signal and the lagging signal, represented as the rising edge and the falling edge of an under-test pulse, are inputted to a first input end 111 and a second input end 112 of the on-chip jitter measurement unit, respectively. Specifically, the leading signal and the lagging signal, inputted to the first input end 111 and the second input end 112, are sequentially processed by a plurality of inverters 121˜12N with a delay time Ts and a plurality of inverters 131˜13N with a delay time Tf and thereby corporately triggering a plurality of D flip-flops 141˜14N, respectively; wherein Ts is greater than Tf. Thus, the under-test time difference between the leading signal and the lagging signal decreases with the number of inverter; and eventually the pulse width of the under-test pulse is measured based on the digital code, represented as the time difference between the leading signal and the lagging signal and obtained by an encoder 15, when the time difference between the leading signal and the lagging signal as well as the outputs of the D flip-flops 141˜14N are converted from a positive value into a negative value. However, due to the manufacture process, voltage and temperature variations, the conventional means for the on-chip jitter measurement unit as described above may not accurately measure the pulse width if the frequency of the under-test pulse increases to a specific level. Even when some other existing or conventional technical means, such as using the timing amplifier to extend the pulse width of the pulse, are introduced for accurately measuring the decreasing the pulse width, the uncertainty resulted from the manufacture process, voltage and temperature variations still cannot be eliminated effectively.